User:WillWare/Xilinx Verilog Ubuntu

This page is about designing programmable hardware in the Verilog hardware description language, using Xilinx devices and design software, on an Ubuntu platform. I am running Ubuntu 10.04 (Lucid) as of this writing.

Here are resources that might help in places where I neglect things.

http://www.digilentinc.com/Data/Documents/Tutorials/Xilinx%20ISE%20WebPACK%20Verilog%20Tutorial.pdf
http://ece.wpi.edu/~rjduck/Spartan3_Tutorial.pdf

Installing the Xilinx tools

The first step is to go to the Xilinx website and get a copy of their design tool ISE. The download is enormous and takes quite a while even with a fast Internet connection. The version I am working with is Xilinx_ISE_DS_Lin_13.1_O.40d.1.1.tar. Unpack it and run the xsetup program.

cd /opt
tar xf /path/to/Xilinx_ISE_DS_Lin_13.1_O.40d.1.1.tar
/opt/Xilinx_ISE_DS_Lin_13.1_O.40d.1.1/xsetup

During this process, you will be sent back to the Xilinx website to pick up a license file, Xilinx.lic. It's a good idea to put that in a directory called $HOME/.Xilinx. I don't remember all the details of what that involved, but it was free. It took a while to figure out what they wanted me to do, and I found it a frustrating process, but I was happy with the end result.

Beginning a project

Once all that's out of the way, you can run

/opt/Xilinx/13.1/ISE_DS/ISE/bin/lin/ise &

which will bring up the Xilinx Verilog IDE. This is an Eclipse derivative so a general familiarity with Eclipse is helpful at this point.

Selecting a top-level module

Your Verilog source file should include a module with inputs and outputs, something like this. This will be your top-level module, using instances of other modules. Starting with an example from an online Verilog tutorial, I added a top-level module that could be synthesized.

module synthesizable(a, b, c, out1, out2, out3, out4);
   input    a, b, c;
   output   out1, out2, out3, out4;
	mux_beh_2 mod1 (out1, c, a, b);
	mux_beh   mod2 (out2, c, a, b);
	mux_func  mod3 (out3, c, a, b);
	mux_gate  mod4 (out4, c, a, b);
endmodule

On the left side of the screen where there are radio buttons for "View" called "Implementation" and "Simulation", and you want to select "Implementation". Select the "Design" tab at the bottom left. Look for the name of your top-level module in the project hierarchy. There should be a triangle of dots to the left of the module name. (If you look closely, they're not really dots, they're iconic diagrams of chips.) If the dots aren't there, right-click on the name and then click "Set as Top Module".

Specify the pinout of your device

Create a file with a name like mypinout.ucf. The "ucf" extension is important. A very simple example looks like this.

NET "a" LOC="P3";
NET "b" LOC="P4";
NET "c" LOC="P5";
NET "out1" LOC="P6";
NET "out2" LOC="P9";
NET "out3" LOC="P10";
NET "out4" LOC="P12";

It's going to be important to check the device data sheet and confirm that each of these pin numbers is really an input or output on the device. The UCF file (User Constraints File) can include other kinds of constraints which are discussed in Xilinx's online docs.

Choosing a device and creating a programming file

Right-click on the name of the top-level module and choose "Design properties...". In the "Project Settings" area, notice there are fields for "Family", "Device", "Package", and "Speed". Set all these for the device you are using. FPGAs will produce a *.bit programming file. CPLDs will produce a *.jed programming file.

The green triangle on the left edge of the screen is a control called "Implement Top Module". Click that and let magic happen for a minute or two. If you're programming a CPLD, you'll get a *.jed file as a result of this process. If you're programming an FPGA, you need to perform one additional step, which is to right-click on "Create Programming File" in the lower left, which will be visible if the "Design" tab is selected at the bottom and "View" is set to "Implementation".