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User:Ben.d.zimmer/sandbox

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I'm messing around with expanding the article for HLT to feature summaries of the HLT instruction on other architectures. So I think I'm going to use the same format as this table that was in the NOP article.

CPU architecture Mnemonic Bytes Opcode Notes
Intel x86 CPU family NOP 1; 1–9 for i686 0x90; 0x0f 0x1f[1] The NOP instruction on the x86 CPU family is actually XCHG EAX, EAX (resulting the same opcode 0x90) - the instruction without any effect.
Intel 8051 / MCS-51 family NOP 1 0x00
ARM NOP 4 0x00000000 This stands for andeq r0, r0, r0 which has no effect at all. The assembly instruction nop will most likely expand to mov r0, r0 which is encoded 0x01A00000.[2]
MIPS NOP 4 0x00000000
MIPS-X NOP 4 0x60000019 (extended opcode for add r0,r0,r0)
MMIX SWYM 4 0xfd****** SWYM stands for “Sympathize with your machinery.” The * digits can be chosen arbitrarily.
Motorola 68000 family NOP 2 0x4e71
MOS Technology 65xx NOP 1 0xea NOP consumes two clock cycles.  Undefined opcodes in the NMOS versions of the 65xx family were converted to be NOPs of varying instruction lengths and cycle times in the 65C02.
PowerPC NOP 4 0x60000000 (extended opcode for ori r0,r0,0)
PIC microcontroller NOP 12 bits 0b000000000000
SPARC NOP 4 0x01000000
Z80 NOP 1 0x00
  1. ^ "Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference Manual". Retrieved 2007-07-13.
  2. ^ ARM Information Center - nop