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List of abbreviations (help):
- D
- Edit made at Wikidata
- r
- Edit flagged by ORES
- N
- New page
- m
- Minor edit
- b
- Bot edit
- (±123)
- Page byte size change
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22 May 2024
- diffhist Intel i860 06:28 +21 Guy Harris talk contribs (The page for that type of ISA is load-store architecture; call it that.)
- diffhist Intel 8087 04:37 +179 170.83.77.181 talk
21 May 2024
- diffhist Whiskey Lake 21:39 −15 BryceMW-CA talk contribs (Update instruction set) Tag: Visual edit
- diffhist Central processing unit 18:38 −35 Dhrm77 talk contribs (rv overlinking) Tag: Undo
- diffhist m Module:Pagetype 17:35 +216 MSGJ talk contribs (fix for files and interface messages which do exist but are not stored locally)
- diffhist m Central processing unit 16:37 +5 Rats5600 talk contribs (Added "(CPU)") Tags: Reverted Visual edit Mobile edit Mobile web edit
- diffhist m Central processing unit 16:32 −6 Rats5600 talk contribs (Link fix) Tags: Reverted Visual edit Mobile edit Mobile web edit
- diffhist m Central processing unit 16:31 +22 Rats5600 talk contribs (Added links) Tags: Reverted Visual edit Mobile edit Mobile web edit
- diffhist m Central processing unit 16:29 +14 Rats5600 talk contribs (Added links) Tags: Reverted Visual edit Mobile edit Mobile web edit
- diffhist Xeon 15:07 +402 BryceMW-CA talk contribs (Turns out that there are a lot of infoboxes to update) Tag: Visual edit
- diffhist Xeon 14:57 +12 BryceMW-CA talk contribs (All Xeons support 16-bit mode (other than Xeon Phi which is a completely different thing with a different page)) Tag: Visual edit
- diffhist m Sandy Bridge 10:58 +1 Awkitsune talk contribs (→Mobile platform: Fix typos) Tag: Visual edit
- diffhist Meltdown (security vulnerability) 07:23 +19 Ost316 talk contribs (c/e) Tag: Visual edit
- diffhist Meltdown (security vulnerability) 07:20 +54 Ost316 talk contribs (Filled in 4 bare reference(s) with reFill 2 | Cleaned up using AutoEd)
- diffhist Meltdown (security vulnerability) 07:14 −4 Ost316 talk contribs (WP:AWB WP:CHECKWIKI 16/90/91 cleanup, et. al., typo(s) fixed: newly- → newly , final outcome → outcome, 2017-5715 → 2017–5715) Tag: AWB
- diffhist m Intel Core 03:26 +31,525 TornadoLGS talk contribs (Reverted edit by 112.202.99.92 (talk) to last version by ThisUsernameThatIsNowTaken) Tag: Rollback
- diffhist Intel Core 03:25 −31,525 112.202.99.92 talk (Heidi's POOL HALL: We Knock Your Balls Around!) Tags: Reverted possible vandalism
- diffhist m Xeon 03:25 +18,681 TornadoLGS talk contribs (Reverted edit by 112.202.99.92 (talk) to last version by Beland) Tag: Rollback
- diffhist Xeon 03:24 −18,681 112.202.99.92 talk (Heidi's POOL HALL: We Knock Your Balls Around!) Tags: Reverted possible vandalism blanking
- diffhist Spectre (security vulnerability) 02:05 +60 2603:6081:8401:110:5ec4:2df0:dc6c:73 talk (→Immune hardware: Add x86 chips)
- diffhist IA-32 00:07 −12 74.89.227.168 talk
- diffhist IA-32 00:07 +1 74.89.227.168 talk
20 May 2024
- diffhist m List of Intel Core processors 23:58 −1 Maxeto0910 talk contribs (no sentence) Tag: Visual edit
- diffhist IA-32 22:13 −160 74.89.227.168 talk
- diffhist Module:Pagetype/rfd 13:04 +27 MSGJ talk contribs (+Rfd-NPF/core)
- diffhist Module:Pagetype/rfd 13:03 +22 MSGJ talk contribs (+Rfd-NPF, seen on West Ardougne)
19 May 2024
- diffhist Memory controller 23:02 −171 Kvng talk contribs (start review: rm overly detailed rep. rm details handled by Memory refresh)
- diffhist Pentium Dual-Core 18:43 +31 2001:14ba:a846:f000::2000 talk (Article described pentium dual core as using SDRAM (PC100-133), corrected to Double-datarate SDRAM and linked to correct article.) Tag: Visual edit
- diffhist Pentium 18:40 +18 2001:14ba:a846:f000::2000 talk (→Pentium M: CPU architecture FSB speed is listed with "MT/s" transfer speed units, the bus is in-fact a hot rodded P6 chip GPTL and it its clock rate is 400-533Mhz, this is can be expressed as 400MT/s as well, but this causes confusion with P4 and Mobile P4 and later CPUs like Core Solo / Duo and Core 2 Solo / Duo which use DDR FSB technology. This is significant because the P6 chip at the time didn't like non-parity clock rates with memory controllers) Tag: Visual edit
- diffhist Advanced Vector Extensions 17:37 +41 178.67.198.26 talk (→CPUs with AVX-512: Added a time frame of Intel disabling AVX-512 in Alder Lake.)
- diffhist AVX-512 17:33 +6 178.67.198.26 talk (→CPUs with AVX-512: Corrected the year of Intel disabling AVX-512 in Alder Lake.)
- diffhist Module:List 16:45 +78 Pppery talk contribs (Per edit request)
- diffhist m Intel Core 14:19 −7,157 ThisUsernameThatIsNowTaken talk contribs (Removing a wikitable.)
- diffhist Pentium 4 11:50 +44 Mike Novikoff talk contribs (→Microarchitecture: wl)
- diffhist Pentium 4 11:35 −94 Mike Novikoff talk contribs (wl, tidy)
- diffhist List of Intel Xeon processors 10:37 +262 84.250.15.152 talk (Add a new "Raptor Lake-based" section (Xeon E-2400 series))
- diffhist m Spectre (security vulnerability) 10:00 −7 Redrabbyte talk contribs (removed "timing", as spectre and meltdown attacks don't *need* timing side-channels, they're just convenient)
- diffhist m StrongARM 07:19 0 Beland talk contribs (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))
- diffhist m Sandy Bridge 06:44 0 Beland talk contribs (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))
- diffhist m RapidCAD 01:42 0 Beland talk contribs (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))
18 May 2024
- diffhist m Xeon 19:30 0 Beland talk contribs (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))
- diffhist m X86 19:29 0 Beland talk contribs (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))
- diffhist m Westmere (microarchitecture) 19:26 0 Beland talk contribs (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))
- diffhist m Penryn (microarchitecture) 01:32 0 Beland talk contribs (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))
17 May 2024
- diffhist Module:Navbox 21:07 +308 Izno talk contribs (per Template talk:Navbox#Night mode may need explicit color definitions)
- diffhist m X86 16:35 −638 Miken32 talk contribs (remove irrelevant info) Tag: 2017 wikitext editor
- diffhist Yonah (microprocessor) 15:38 +18 BryceMW-CA talk contribs (Fix instruction set) Tag: Visual edit
- diffhist AVX-512 15:23 −59 Michaelmalak talk contribs (→CPUs with AVX-512: Fill in "when" based on already-existing cite)
- diffhist Intel 80186 15:08 +15 Kvng talk contribs (numbers units)
- diffhist AVX-512 14:59 +52 Hexware talk contribs (→CPUs with AVX-512) Tag: 2017 wikitext editor