Related changes

22 May 2024

• diffhist Multi-core processor‎ 17:51 +441‎ ‎Privateeih talk contribs‎ Tag: Visual edit

21 May 2024

• diffhist DDR5 SDRAM‎ 23:26 −110‎ ‎78.0.162.14 talk‎ (When DDR4 was 5-6 years old, DDR5 came out. DDR5 is 4 years old and we're still reading articles like https://www.techreviewer.com/tech-answers/is-ddr5-worth-it/)

20 May 2024

• diffhist m DDR4 SDRAM‎ 20:57 0‎ ‎Shafi ahmed.0 talk contribs‎ (copy edits) Tag: Visual edit
• diffhist m DDR5 SDRAM‎ 09:15 −69‎ ‎Indomitun talk contribs‎ (Got rid of a unwanted link at the start of the page) Tag: Visual edit
• diffhist DDR5 SDRAM‎ 09:14 +86‎ ‎Indomitun talk contribs‎ (added an additional ram speed that’s supported by DDR5 (DDR5-8400)) Tag: Visual edit

19 May 2024

• diffhist Athlon‎ 19:42 −2‎ ‎2001:14ba:a846:f000::2000 talk‎ Tag: Visual edit
• diffhist Athlon‎ 18:34 −36‎ ‎2001:14ba:a846:f000::2000 talk‎ Tag: Visual edit
• diffhist Athlon‎ 18:34 +11‎ ‎2001:14ba:a846:f000::2000 talk‎ (→‎Athlon XP (2001–2003)) Tag: Visual edit
• diffhist Athlon‎ 18:19 −30‎ ‎2001:14ba:a846:f000::2000 talk‎ (→‎Athlon Classic (1999): FSB falsely described as "double-pumped". No, DEC ALPHA EV6 bus is from the mid-1990s and incapable of bit-doubling per clock cycle data transfer modes. STOP VANDALIZING ARTICLES REPLACING "Mhz" wiith "MT/s" ASSUMING SYSTEMS THAT DO NOT HAVE THIS TECHNOLOGY NEED THIS RECENT UNIT OF MEASUREMENT AND ASSUMING THAT FSB HAS ALWAYS MEANT DIRECT ACCESS TO MEMORY CONTROLLER WHICH ISN'T INTEGRATED IN OLDER ARCHITECTURES) Tag: Visual edit
• diffhist Athlon‎ 18:16 +34‎ ‎2001:14ba:a846:f000::2000 talk‎ (XP CPU FSB erroniously described as 266-400MT/s. The Athlon uses DEC ALPHA EV6 CPU bus which is incapable of DDR data transfer. The FSB connects the CPU to the Northbridge, which then has a separate memory controller that talks to the memory chips with DDR transfers. The FSB is not DDR at any point, and the reason why these systems didn't benefit from dual-channel or DDR memory speeds significantly was because of this bottleneck. Only incresing FSB true clockrate increased performance) Tag: Visual edit
• diffhist m Steamroller (microarchitecture)‎ 07:18 0‎ ‎Beland talk contribs‎ (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))

18 May 2024

• diffhist m X86‎ 19:29 0‎ ‎Beland talk contribs‎ (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))
• diffhist m Zen 3‎ 08:49 0‎ ‎Beland talk contribs‎ (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))
• diffhist m Zen (microarchitecture)‎ 08:49 0‎ ‎Beland talk contribs‎ (change U+00B5 to U+03BC (μ) per Unicode standard and MOS:NUM#Specific units - see Unicode compatibility characters (via WP:JWB))

17 May 2024

• diffhist Module:Navbox‎ 21:07 +308‎ ‎Izno talk contribs‎ (per Template talk:Navbox#Night mode may need explicit color definitions)
• diffhist m X86‎ 16:35 −638‎ ‎Miken32 talk contribs‎ (remove irrelevant info) Tag: 2017 wikitext editor
• diffhist Microarchitecture‎ 01:08 +36‎ ‎User-duck talk contribs‎ (This looks like the last good version.) Tag: Manual revert
• diffhist Microarchitecture‎ 00:57 −70‎ ‎User-duck talk contribs‎ (Trying to fix cites.) Tag: Reverted

16 May 2024

• diffhist Microarchitecture‎ 19:51 +34‎ ‎206.125.158.145 talk‎ (changed it back to original to stop Mickey Wathan from all theft of Me Please he is a Halliburton and he stole everything he has from me im a rockefeller and a henderson no blood will ever change that) Tags: Reverted Mobile edit Mobile web edit
• diffhist Zen 4‎ 17:20 +72‎ ‎197.207.150.255 talk‎ Tag: Visual edit
• diffhist m Microarchitecture‎ 15:01 0‎ ‎Beland talk contribs‎ (mu not micro per MOS:NUM#Specific units and Unicode compatibility characters (via WP:JWB))