User contributions for User243422224
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A user with 15 edits. Account created on 18 January 2023.
18 January 2023
- 18:0018:00, 18 January 2023 diff hist −946 Talk:Apple silicon →Sweep of the GPU stats
- 17:5817:58, 18 January 2023 diff hist +132 Apple silicon Thanks for the insight, but online reports from Powermetrics report 1398 MHz. Apple can round up 3.58 TFLOPS to 3.60 TFLOPS. This round their Pro and Max also have 1398 MHz too, which you can calculate from 13.6 TFLOPS. The next possible jump would be 1404 MHz or 1410 MHz, which means 13.65 or 13.7 TFLOPS.
- 01:5501:55, 18 January 2023 diff hist +5 Apple silicon →List of processors: Clarify what kind of FLOPS we're using. If we added F16 FLOPS to the A-series, the massive jump wouldn't seem so confusing.
- 01:1501:15, 18 January 2023 diff hist +109 N User:User243422224 Create bio current
- 01:0901:09, 18 January 2023 diff hist +885 Talk:Apple silicon →Sweep of the GPU stats
- 00:5600:56, 18 January 2023 diff hist −8 Talk:Apple silicon →Sweep of the GPU stats
- 00:5600:56, 18 January 2023 diff hist +333 Talk:Apple silicon →Sweep of the GPU stats
- 00:5400:54, 18 January 2023 diff hist +1 m Apple silicon →List of processors: Visual editor is glitching??? Tag: Visual edit
- 00:5200:52, 18 January 2023 diff hist −25 Apple silicon →List of processors: Fixed another oopsie, table still malformatted Tag: Visual edit
- 00:4800:48, 18 January 2023 diff hist +132 Talk:Apple silicon →Tables are unbelievably bloated.: Reply Tag: Reply
- 00:4300:43, 18 January 2023 diff hist +1 m Talk:Apple silicon →Sweep of the GPU stats: Attempt to correct my typo
- 00:4100:41, 18 January 2023 diff hist +608 Talk:Apple silicon No edit summary
- 00:3600:36, 18 January 2023 diff hist 0 Apple silicon →List of processors: Mistake when counting A14. EU count is a meaningless metric because it says nothing about performance. A core could do 128 Int32 instructions per second or 64 or 128 FP32 instructions per second or 128 Int32 instructions per second. It might even just be dual-dispatching from 2 SIMDs, instead of single-dispatching from 4 SIMDs. SIMDs are 32 threads wide. Tag: Visual edit
- 00:3200:32, 18 January 2023 diff hist +21 Apple silicon →List of processors: FLOPS is 2 (FMA) * 128 * cores * MHz. A14 had more F32 power because they made the F16 ALUs actually be F32 ALUs. That's the reason M1 has 4x the F32 performance, 2x the F16 performance, and 2x the cores, and the exact same clock speed.
- 00:2400:24, 18 January 2023 diff hist +35 Apple silicon →List of processors